A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications

Abstract

This brief presents an all-digital synchronous clock generator with an open-loop architecture, which achieves a fast lock and a wide range for mobile applications. The proposed architecture based on a clock-synchronized delay adopts a multipath delay line, which provides a high resolution and a low deterministic jitter with calibration circuits. A frequency range selector with a locking range moving technique achieves a wide-range operation. The proposed clock generator operates from 100 MHz to 1 GHz with a 14-ps peak-to-peak jitter performance at 1 GHz. The measured lock time is three to ten clock cycles depending on the operating frequency. The clock generator is implemented in a 0.18-mu m CMOS process.