Measurement and Analysis for Residual Warpage of Chip-on-Flex (COF) and Chip-in-Flex (CIF) Packages

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dc.contributor.authorJang, Jae-Wonko
dc.contributor.authorSuk, Kyoung-Limko
dc.contributor.authorPaik, Kyung-Wookko
dc.contributor.authorLee, Soon-Bokko
dc.date.accessioned2013-03-09T00:24:55Z-
dc.date.available2013-03-09T00:24:55Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2012-05-
dc.identifier.citationIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.2, no.5, pp.834 - 840-
dc.identifier.issn2156-3950-
dc.identifier.urihttp://hdl.handle.net/10203/94797-
dc.description.abstractA flip-chip package using adhesive interconnection consists of materials which have different coefficients of thermal expansion (CTE). The package experiences temperature higher than room temperature during the assembly process and is also exposed to the thermal cycling load during its lifetime. As a result, flip-chip packages have residual warpage after completion of the assembly process. Excessive warpage causes various reliability problems. Therefore, residual warpage is an essential factor for evaluating the reliability of electronic packages. In this paper, we evaluated the warpage of chip-on-flex (COF) packages using the moire methods. A chip-in-flex (CIF) package developed to increase the binding force between the chip and the substrate was also evaluated with the same methods. Finite element analysis (FEA) was also performed for comparison with the experimental results. Based on the FEA result, effective design parameters for the CIF package were found to reduce the residual warpage.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectTECHNOLOGY-
dc.subjectSTRESSES-
dc.subjectDESIGN-
dc.subjectMOIRE-
dc.titleMeasurement and Analysis for Residual Warpage of Chip-on-Flex (COF) and Chip-in-Flex (CIF) Packages-
dc.typeArticle-
dc.identifier.wosid000303909300013-
dc.identifier.scopusid2-s2.0-84860860508-
dc.type.rimsART-
dc.citation.volume2-
dc.citation.issue5-
dc.citation.beginningpage834-
dc.citation.endingpage840-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY-
dc.identifier.doi10.1109/TCPMT.2011.2175732-
dc.contributor.localauthorPaik, Kyung-Wook-
dc.contributor.localauthorLee, Soon-Bok-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorChip-in-flex package-
dc.subject.keywordAuthorchip-on-flex package-
dc.subject.keywordAuthorfinite element analysis-
dc.subject.keywordAuthorresidual warpage-
dc.subject.keywordAuthorshadow moire-
dc.subject.keywordAuthorTwyman/Green interferometry-
dc.subject.keywordPlusTECHNOLOGY-
dc.subject.keywordPlusSTRESSES-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusMOIRE-
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