Measurement and Analysis for Residual Warpage of Chip-on-Flex (COF) and Chip-in-Flex (CIF) Packages

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A flip-chip package using adhesive interconnection consists of materials which have different coefficients of thermal expansion (CTE). The package experiences temperature higher than room temperature during the assembly process and is also exposed to the thermal cycling load during its lifetime. As a result, flip-chip packages have residual warpage after completion of the assembly process. Excessive warpage causes various reliability problems. Therefore, residual warpage is an essential factor for evaluating the reliability of electronic packages. In this paper, we evaluated the warpage of chip-on-flex (COF) packages using the moire methods. A chip-in-flex (CIF) package developed to increase the binding force between the chip and the substrate was also evaluated with the same methods. Finite element analysis (FEA) was also performed for comparison with the experimental results. Based on the FEA result, effective design parameters for the CIF package were found to reduce the residual warpage.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2012-05
Language
English
Article Type
Article
Keywords

TECHNOLOGY; STRESSES; DESIGN; MOIRE

Citation

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.2, no.5, pp.834 - 840

ISSN
2156-3950
DOI
10.1109/TCPMT.2011.2175732
URI
http://hdl.handle.net/10203/94797
Appears in Collection
MS-Journal Papers(저널논문)ME-Journal Papers(저널논문)
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