DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, SungRok | ko |
dc.contributor.author | Seo, SangHo | ko |
dc.contributor.author | Huang M.L. | ko |
dc.contributor.author | Park, Sin Chong | ko |
dc.date.accessioned | 2013-03-08T23:54:26Z | - |
dc.date.available | 2013-03-08T23:54:26Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.46, no.11, pp.800 - U101 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/94717 | - |
dc.description.abstract | Presented is a software cyclic redundancy check (CRC) parallel computation scheme for the realisation of a high-speed wireless communication system on a multi-processor design platform. The proposed CRC generation scheme was applied to the IEEE 802.11n WLAN system. As a result, the proposed CRC scheme is capable of meeting tight latency constraint to achieve 144 Mbit/s throughput at a processor frequency less than 200 MHz, when evaluated with register-transfer-level simulation. | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Multi-processor based CRC computation scheme for high-speed wireless LAN design | - |
dc.type | Article | - |
dc.identifier.wosid | 000279091200045 | - |
dc.identifier.scopusid | 2-s2.0-77952984332 | - |
dc.type.rims | ART | - |
dc.citation.volume | 46 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 800 | - |
dc.citation.endingpage | U101 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el.2010.0145 | - |
dc.contributor.localauthor | Park, Sin Chong | - |
dc.type.journalArticle | Article | - |
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