Multi-processor based CRC computation scheme for high-speed wireless LAN design

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Presented is a software cyclic redundancy check (CRC) parallel computation scheme for the realisation of a high-speed wireless communication system on a multi-processor design platform. The proposed CRC generation scheme was applied to the IEEE 802.11n WLAN system. As a result, the proposed CRC scheme is capable of meeting tight latency constraint to achieve 144 Mbit/s throughput at a processor frequency less than 200 MHz, when evaluated with register-transfer-level simulation.
Publisher
INST ENGINEERING TECHNOLOGY-IET
Issue Date
2010
Language
English
Article Type
Article
Citation

ELECTRONICS LETTERS, v.46, no.11, pp.800 - U101

ISSN
0013-5194
DOI
10.1049/el.2010.0145
URI
http://hdl.handle.net/10203/94717
Appears in Collection
EE-Journal Papers(저널논문)
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