Pulsed-Latch Circuits: A New Dimension in ASIC Design
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Shin, Young-Soo | ko |
| dc.contributor.author | Paik, Seung-Whun | ko |
| dc.date.accessioned | 2013-03-08T22:13:15Z | - |
| dc.date.available | 2013-03-08T22:13:15Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2011 | - |
| dc.identifier.citation | IEEE DESIGN TEST OF COMPUTERS, v.28, pp.50 - 57 | - |
| dc.identifier.issn | 0740-7475 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/94458 | - |
| dc.description.abstract | Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher performance and lower power consumption within a conventional ASIC design environment. This article identifies a design methodology and tools for pulsed-latch ASICs to complement this environment. The authors review potential solutions and provide quantitative results to assess the effectiveness of pulsed-latch circuits. | - |
| dc.language | English | - |
| dc.publisher | IEEE COMPUTER SOC | - |
| dc.subject | LOW-POWER | - |
| dc.subject | MICROPROCESSOR | - |
| dc.title | Pulsed-Latch Circuits: A New Dimension in ASIC Design | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000298208000009 | - |
| dc.identifier.scopusid | 2-s2.0-80053629025 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 28 | - |
| dc.citation.beginningpage | 50 | - |
| dc.citation.endingpage | 57 | - |
| dc.citation.publicationname | IEEE DESIGN TEST OF COMPUTERS | - |
| dc.contributor.localauthor | Shin, Young-Soo | - |
| dc.type.journalArticle | Article | - |
| dc.subject.keywordAuthor | design and test | - |
| dc.subject.keywordAuthor | high performance | - |
| dc.subject.keywordAuthor | low power | - |
| dc.subject.keywordAuthor | pulsed latch | - |
| dc.subject.keywordAuthor | pulsed-latch ASIC methodology | - |
| dc.subject.keywordPlus | LOW-POWER | - |
| dc.subject.keywordPlus | MICROPROCESSOR | - |
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