Pulsed-Latch Circuits: A New Dimension in ASIC Design

Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher performance and lower power consumption within a conventional ASIC design environment. This article identifies a design methodology and tools for pulsed-latch ASICs to complement this environment. The authors review potential solutions and provide quantitative results to assess the effectiveness of pulsed-latch circuits.
Publisher
IEEE COMPUTER SOC
Issue Date
2011
Language
ENG
Keywords

LOW-POWER; MICROPROCESSOR

Citation

IEEE DESIGN TEST OF COMPUTERS, v.28, pp.50 - 57

ISSN
0740-7475
URI
http://hdl.handle.net/10203/94458
Appears in Collection
EE-Journal Papers(저널논문)
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