DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jang, Yongho | ko |
dc.contributor.author | Kim, Jungsoo | ko |
dc.contributor.author | Kyung, Chong-Min | ko |
dc.date.accessioned | 2013-03-08T18:46:11Z | - |
dc.date.available | 2013-03-08T18:46:11Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.29, pp.2041 - 2045 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | http://hdl.handle.net/10203/93946 | - |
dc.description.abstract | Crossbar switch network has an increasing impact on such critical measures as throughput, latency, area, and power consumption of complex system-on-chip as technology scales to deep submicrometer. With high clock frequency crossbar switch network design, global wire delay and pipeline registers inserted for throughput are important because they affect area, frequency, and power consumption of the chip. The traffic congestion is also a very important factor because it leads to the lowering of throughput of the crossbar switch network. In this paper, we present a topology synthesis method for the low-power cascaded crossbar switch network satisfying the given bandwidth, latency, frequency, and area constraints. Unlike previous papers, our paper considers wire delay, traffic congestion, and pipeline register insertion at the same time. Experimental results show that the topologies optimized for power consumption for a given clock frequency consume less power than existing methods by up to 38.04%. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | BUS MATRIX | - |
dc.subject | ARCHITECTURES | - |
dc.subject | DESIGN | - |
dc.title | Topology Synthesis for Low Power Cascaded Crossbar Switches | - |
dc.type | Article | - |
dc.identifier.wosid | 000284417400016 | - |
dc.identifier.scopusid | 2-s2.0-78649341648 | - |
dc.type.rims | ART | - |
dc.citation.volume | 29 | - |
dc.citation.beginningpage | 2041 | - |
dc.citation.endingpage | 2045 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.identifier.doi | 10.1109/TCAD.2010.2072730 | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.nonIdAuthor | Jang, Yongho | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Crossbar switch network | - |
dc.subject.keywordAuthor | topology synthesis | - |
dc.subject.keywordAuthor | traffic congestion | - |
dc.subject.keywordPlus | BUS MATRIX | - |
dc.subject.keywordPlus | ARCHITECTURES | - |
dc.subject.keywordPlus | DESIGN | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.