Asynchronous layered interface of multimedia SoCs for multiple outstanding transactions

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In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.
Publisher
SPRINGER,
Issue Date
2007-03
Language
English
Article Type
Article; Proceedings Paper
Citation

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, v.46, no.2-3, pp.133 - 151

ISSN
0922-5773
DOI
10.1007/s11265-006-0019-4
URI
http://hdl.handle.net/10203/93259
Appears in Collection
GT-Journal Papers(저널논문)
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