Tensile-strained germanium CMOS integration on silicon

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Monolithic integration of tensile-strained Si/Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness similar to 14 angstrom) HfO2 gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to similar to 0.67% and exhibits a peak hole mobility of 250 cm(2)/V. S which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.
Publisher
IEEE
Issue Date
2007-12
Language
English
Article Type
Article
Keywords

SURFACE PASSIVATION; GE

Citation

IEEE ELECTRON DEVICE LETTERS, v.28, no.12, pp.1117 - 1119

ISSN
0741-3106
DOI
10.1109/LED.2007.909836
URI
http://hdl.handle.net/10203/92711
Appears in Collection
EE-Journal Papers(저널논문)
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