Geometry engine architecture with early backface culling hardware

Abstract

Most graphics accelerators waste valuable performance on transforming invisible vertices. To solve this problem, we have performed backface culling (BFC) earlier than transform and lighting (TnL). This paper proposes a survived vertex decision (SVD) algorithm to remove invisible vertices, and also suggests a geometry engine architecture that performs the early BFC with the SVD algorithm. This approach requires less hardware overhead. The SVD algorithm discards a vertex only if all triangles sharing that vertex are invisible in the mesh representing triangle lists or strips. The dedicated hardware performing the early BFC guarantees better performance in our approach, since it runs with the vertex engines in parallel. Particularly for a standalone engine, we introduce a unified architecture named the VP-Engine, which can perform the same tasks of the vertex engine and also handle the early BFC. Our architecture is designed using an instruction set simulator with a C + + library for cycle-accurate simulations. The early BFC removes half of the vertices that are transformed in the conventional approach, and as such the performance of our proposed architecture is twice as fast at maximum. Even with the sequential operations of early BFC and typical TnL, the VP-Engine is faster while the length of a vertex program is larger than 24. (c) 2005 Elsevier Ltd. All rights reserved.