Accelerating verification with reusable testbench

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The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2006-02
Language
English
Article Type
Article
Citation

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E89D, pp.853 - 856

ISSN
0916-8532
URI
http://hdl.handle.net/10203/90789
Appears in Collection
EE-Journal Papers(저널논문)
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