Designing on-chip network based on optimal latency criteria

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A new chip design paradigm, so called Network on Chip, has been introduced based on the demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks. The Network on Chip design not only requires the good performance but also the minimization of several physical constraints such as the network latency, the used area as well as the power consumption of design. This paper analyzes the average latency of heterogeneous Network on Chip architectures in which the shortest path routing algorithm is applied. This average latency includes the queuing latency and the wire latency, and is calculated for general cases of allocating IPs onto the fixed generic switching architectures such as 2-D Mesh and Fat-Tree. With different allocation schemes of IPs, the network has different average latencies. Hence, this article presents an optimal search that adopts the Branch and Bound algorithm to find out the optimal mapping scheme to achieve the minimal network latency. This algorithm automatically map the desired IPs onto the target Network on Chip architecture with the criteria of lowest network latency. Some experiments of On Chip Multiprocessor Network application are simulated. The results show that the network latency is significantly saved with the optimized allocation scheme for the several cases of generic architectures of On Chip Multiprocessor Network application.
Publisher
SPRINGER-VERLAG BERLIN
Issue Date
2005
Language
English
Article Type
Article; Proceedings Paper
Citation

EMBEDDED SOFTWARE AND SYSTEMS, PROCEEDINGS BOOK SERIES: LECTURE NOTES IN COMPUTER SCIENCE, v.3820, pp.287 - 298

ISSN
0302-9743
URI
http://hdl.handle.net/10203/90788
Appears in Collection
EE-Journal Papers(저널논문)
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