Frequency-controllable image rejection down CMOS mixer

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This paper presents a frequency-controllable image rejection mixer in heterodyne architecture for 2 GHz applications based on TSMC 0.18 mu m CMOS technology. The designed mixer uses a notch filter to suppress the image signal and allows precise tuning the image frequencies. An image rejection of 20-70 dB is obtained in a 200 MHz of bandwidth. The simulation results show single-side band (SSB) NF is improved 3.7 dB, the voltage conversion gain of 14.7 dB, improved by more than 4 dB. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.34mW.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2005-12
Language
English
Article Type
Article; Proceedings Paper
Citation

IEICE TRANSACTIONS ON ELECTRONICS, v.E88C, pp.2322 - 2324

ISSN
0916-8524
URI
http://hdl.handle.net/10203/87929
Appears in Collection
EE-Journal Papers(저널논문)
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