Demonstration of L-g similar to 55 nm pMOSFETs with Si/Si0.25Ge0.75/Si channels, high I-on/I-off (> 5 x 10(4)), and controlled short channel effects (SCEs)

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dc.contributor.authorLee, SHko
dc.contributor.authorMajhi, Pko
dc.contributor.authorOh, Jko
dc.contributor.authorSassman, Bko
dc.contributor.authorYoung, Cko
dc.contributor.authorBowonder, Ako
dc.contributor.authorLoh, WYko
dc.contributor.authorChoi, KJko
dc.contributor.authorCho, Byung Jinko
dc.contributor.authorLee, HDko
dc.contributor.authorKirsch, Pko
dc.contributor.authorHarris, HRko
dc.contributor.authorTsai, Wko
dc.contributor.authorDatta, Sko
dc.contributor.authorTseng, HHko
dc.contributor.authorBanerjee, SKko
dc.contributor.authorJammy, Rko
dc.date.accessioned2013-03-06T16:20:35Z-
dc.date.available2013-03-06T16:20:35Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2008-09-
dc.identifier.citationIEEE ELECTRON DEVICE LETTERS, v.29, no.9, pp.1017 - 1020-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10203/87570-
dc.description.abstractHigh-performance sub-60 nm Si/SiGe (Ge: similar to 75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with similar to 1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (L-g) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (I-on/I-off) ratio (similar to 5 x 10(4) at 55-nm L-g). The intrinsic gate delay of these heterostructures is similar to 3 ps at I-on/I-off similar to 10(4). OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short Lg devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.-
dc.languageEnglish-
dc.publisherIEEE-
dc.subjectHIGH-PERFORMANCE PMOSFETS-
dc.subjectQUANTUM-WELLS-
dc.subjectP-MOSFETS-
dc.subjectTECHNOLOGY-
dc.subjectSILICON-
dc.subjectLAYERS-
dc.titleDemonstration of L-g similar to 55 nm pMOSFETs with Si/Si0.25Ge0.75/Si channels, high I-on/I-off (> 5 x 10(4)), and controlled short channel effects (SCEs)-
dc.typeArticle-
dc.identifier.wosid000259573400015-
dc.identifier.scopusid2-s2.0-50649109671-
dc.type.rimsART-
dc.citation.volume29-
dc.citation.issue9-
dc.citation.beginningpage1017-
dc.citation.endingpage1020-
dc.citation.publicationnameIEEE ELECTRON DEVICE LETTERS-
dc.identifier.doi10.1109/LED.2008.2002073-
dc.contributor.localauthorCho, Byung Jin-
dc.contributor.nonIdAuthorLee, SH-
dc.contributor.nonIdAuthorMajhi, P-
dc.contributor.nonIdAuthorOh, J-
dc.contributor.nonIdAuthorSassman, B-
dc.contributor.nonIdAuthorYoung, C-
dc.contributor.nonIdAuthorBowonder, A-
dc.contributor.nonIdAuthorLoh, WY-
dc.contributor.nonIdAuthorChoi, KJ-
dc.contributor.nonIdAuthorLee, HD-
dc.contributor.nonIdAuthorKirsch, P-
dc.contributor.nonIdAuthorHarris, HR-
dc.contributor.nonIdAuthorTsai, W-
dc.contributor.nonIdAuthorDatta, S-
dc.contributor.nonIdAuthorTseng, HH-
dc.contributor.nonIdAuthorBanerjee, SK-
dc.contributor.nonIdAuthorJammy, R-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorband-to-band tunneling (BTBT)-
dc.subject.keywordAuthoreffective oxide thickness (EOT)-
dc.subject.keywordAuthorintrinsic gate delay-
dc.subject.keywordAuthorshort channel effect (SCE)-
dc.subject.keywordAuthorsilicon germanium (SiGe)-
dc.subject.keywordPlusHIGH-PERFORMANCE PMOSFETS-
dc.subject.keywordPlusQUANTUM-WELLS-
dc.subject.keywordPlusP-MOSFETS-
dc.subject.keywordPlusTECHNOLOGY-
dc.subject.keywordPlusSILICON-
dc.subject.keywordPlusLAYERS-
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