Multi-layer high-kappa interpoly dielectric for floating gate flash memory devices

We present a systematic simulation and experimental study of tunneling leakage current of the interpoly dielectric (IPD) layer in a floating gate (FG) type flash memory. IPD layers with different structural and material combinations such as HfLaO and 4% Tb-doped HfO2 were studied. It is shown that compared with a conventional Al2O3-HfO2-Al2O3 high-low-high barrier structure, the HfO2-Al2O3-HfO2 multilayer IPD stack with a low-high-low barrier structure has a lower leakage current due to the longer effective electron tunneling distance. Results also show that multilayer IPD structure has advantage of better thermal stability compared to the single layer IPD. Further work with simulations and experiments results suggest that the presence of a thin interfacial layer between polysilicon FG and IPD can increase the magnitude of leakage current by two or three orders. Nitridation of polysilicon floating gate reduced the leakage current by around two orders of magnitude at a constant equivalent oxide thickness. This is due to the elimination of the interfacial layer between polysilicon and high-kappa IPD. (c) 2008 Elsevier Ltd. All rights reserved.
Publisher
PERGAMON-ELSEVIER SCIENCE LTD
Issue Date
2008-04
Language
ENG
Citation

SOLID-STATE ELECTRONICS, v.52, pp.564 - 570

ISSN
0038-1101
DOI
10.1016/j.sse.2008.01.010
URI
http://hdl.handle.net/10203/87544
Appears in Collection
EE-Journal Papers(저널논문)
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