In this paper, we propose an architecture level analysis of the frame buffer access pattern of the recent 3D graphics accelerators that utilize multiple pipelined rendering engines. Based on this analysis, we propose an energy efficient memory address converter for an SoC-based 3D graphics system with an SDRAM frame buffer. About 30% of energy reduction and 20% of runtime reduction is obtained with the address converter. With dynamic power management feature of SDRAM, the energy gains increase to about 50%. The energy and runtime gains are generated by an access pattern analysis based division and assignment of frame buffer onto multiple memory modules. With this proposed access pattern analysis, a frame buffer system optimization of an IP-based 3D graphics accelerator can be performed at early architecture design level.