Image-rejection CMOS low-noise amplifier design optimization techniques

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This paper reviews and analyzes two reported' image-rejection (IR) low-noise amplifier (LNA) design, techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18-mum CMOS-technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, lower than 1.5-dB noise figure, -5-dBm input-referred third-order intercept point and an IR of 26 dB.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2005-02
Language
English
Article Type
Article; Proceedings Paper
Keywords

RECEIVER; RF

Citation

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.53, pp.538 - 547

ISSN
0018-9480
URI
http://hdl.handle.net/10203/87304
Appears in Collection
EE-Journal Papers(저널논문)
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