P-type floating gate for retention and P/E window improvement of flash memory devices

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A Flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) V-th window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled Flash memory cells. Both device simulation and experimental verification are presented.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2007-08
Language
English
Article Type
Article
Keywords

EEPROMS

Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.54, no.8, pp.1910 - 1917

ISSN
0018-9383
DOI
10.1109/TED.2007.900680
URI
http://hdl.handle.net/10203/86952
Appears in Collection
EE-Journal Papers(저널논문)
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