Instruction based synthesizable testbench architecture

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This paper presents a synthesizable testbench architecture based on a defined instruction for standalone mode verification. A set of instructions describes transitions of a signal. The set of instructions can be changed easily to describe different signal transitions by loading the different set of instructions on emulator's memory. The proposed testbench enables a fast emulation and increases flexibility and reusability by using an instruction set. To prove the performance of instruction based synthesizable testbench, we verified Bluetooth and IEEE 802.11a PHY baseband systems and compared their performance with those of co-sim mode and modified co-sim mode emulation.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2006-05
Language
English
Article Type
Article
Citation

IEICE TRANSACTIONS ON ELECTRONICS, v.E89C, pp.653 - 657

ISSN
0916-8524
DOI
10.1093/ietele/e89-c.5.653
URI
http://hdl.handle.net/10203/86945
Appears in Collection
EE-Journal Papers(저널논문)
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