New through-wafer via interconnections with thick oxidized porous silicon sidewall via

Abstract

In this paper, we present the detailed fabrication process and high-frequency characterization of a new silicon through-wafer via interconnection and a low pass filter module flip-chip bonded to these via interconnections. An oxide liner of 18 mu m thick for the via was fabricated on a complementary metal-oxide-semi conductor (CMOS)-grade low-resistivity 5 Omega.cm silicon wafer using the oxidized porous silicon (OPS) process. The through-wafer vias were filled with copper by electroplating. For a via interconnection of 240 mu m length and 70 mu m diameter, the series inductance and resistance are 0.079 nH and 0.059 Omega each. A coplanar waveguide (CPW) and a RF low pass filter (LPF) module were assembled on this through-wafer via interconnection substrate.