Four-ary tree-based barrier synchronization for 2D meshes without nonmember involvement

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dc.contributor.authorMoh, Sko
dc.contributor.authorYu, CSko
dc.contributor.authorLee, Bko
dc.contributor.authorYoun, HYko
dc.contributor.authorHan, Dongsooko
dc.contributor.authorLee, DongManko
dc.date.accessioned2013-03-05T02:24:54Z-
dc.date.available2013-03-05T02:24:54Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2001-08-
dc.identifier.citationIEEE TRANSACTIONS ON COMPUTERS, v.50, no.8, pp.811 - 823-
dc.identifier.issn0018-9340-
dc.identifier.urihttp://hdl.handle.net/10203/85037-
dc.description.abstractThis paper proposes a Barrier Tree for Meshes (BTM) to minimize the barrier synchronization latency for two-dimensional (2D) meshes. The proposed BTM scheme has two distinguishing features. First, the synchronization tree is 4-ary. The synchronization latency of the BTM scheme is asymptotically Theta (log(4) n), while that of the fastest scheme reported in the literature is bounded between Omega (log(3) n) and O(n(1/2)), where n is the number of member nodes. Second, nonmember nodes are neither involved in the construction of a BTM nor actively participate in the synchronization operations, which avoids interference among different process groups during synchronization. This not only results in low setup overhead, but also reduces the synchronization latency. The low setup overhead is particularly effective for the dynamic process model provided in MPI-2. Extensive simulation study shows that, for up to 64 x 64 meshes, the BTM scheme results in about 40 similar to 70 percent shorter synchronization latency and is more scalable than conventional schemes.-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.subjectWORMHOLE-
dc.subjectCOMMUNICATION-
dc.subjectIMPLEMENTATION-
dc.subjectMULTICOMPUTERS-
dc.subjectNETWORKS-
dc.titleFour-ary tree-based barrier synchronization for 2D meshes without nonmember involvement-
dc.typeArticle-
dc.identifier.wosid000170643500005-
dc.identifier.scopusid2-s2.0-0035415855-
dc.type.rimsART-
dc.citation.volume50-
dc.citation.issue8-
dc.citation.beginningpage811-
dc.citation.endingpage823-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPUTERS-
dc.contributor.localauthorHan, Dongsoo-
dc.contributor.localauthorLee, DongMan-
dc.contributor.nonIdAuthorMoh, S-
dc.contributor.nonIdAuthorYu, CS-
dc.contributor.nonIdAuthorLee, B-
dc.contributor.nonIdAuthorYoun, HY-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordAuthorbarrier synchronization-
dc.subject.keywordAuthorhardware-supported barriers-
dc.subject.keywordAuthorcommunication latency-
dc.subject.keywordAuthorwormhole routing-
dc.subject.keywordAuthorMPI-
dc.subject.keywordPlusWORMHOLE-
dc.subject.keywordPlusCOMMUNICATION-
dc.subject.keywordPlusIMPLEMENTATION-
dc.subject.keywordPlusMULTICOMPUTERS-
dc.subject.keywordPlusNETWORKS-
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