A 5.2-GHz LNA in 0.35-mu m CMOS utilizing inter-stage series resonance and optimizing the substrate resistance

A current-reused two-stage low-noise amplifier (LNA) topology is proposed, which adopts a series inter-stage resonance and optimized substrate resistance of individual transistors. The characteristics of the series inter-stage resonance in gain enhancement are analyzed and compared with other alternatives. The contradicting effects of substrate resistance on common-source and common-gate amplifiers are analyzed and proposed guidelines for high-gain operation. The LNA is implemented based on a 0.35-mum CMOS technology for 5.2-GHz wireless LAN applications. Measurements show 19.3 dB of power gain, 2.45 dB of noise figure, and 13.2 dBm of output IP3, respectively, for the dc power supply of 8 mA and 3.3 V.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2003-04
Language
ENG
Keywords

FRONT-END; RECEIVER

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.38, pp.669 - 672

ISSN
0018-9200
DOI
10.1109/JSSC.2003.809523
URI
http://hdl.handle.net/10203/84675
Appears in Collection
EE-Journal Papers(저널논문)
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