Efficient ABR service engine for ATM networks An Efficient ABR Service Engine for ATM Network

In the recent ATM Forum activities, considerable efforts have been focused on the available bit rate (ABR) service, which enables maximal link utilisation in the ATM network. An ABR service engine is presented, which provides optimal hardware solution for all functions of the ABR service algorithm. To compute congestion control information, the ABR service engine consists of an ER engine, a queueing connection (QC) estimation unit, and a cell decoder/encoder (CIDE). To implement the algorithm efficiently, the new engine uses the following schemes. The ER is periodically computed in order to provide sufficient computation time. Through a periodical computation, a low cell delay is achieved when cells pass through the ABR service engine. Using a QC corrector, the implementation of the QC estimation unit is simplified. A register control block efficiently controls internal variables, and arithmetic units are designed for precise computation with simple architecture. Therefore, the ABR service engine is very small in size and provides high speed. In addition, it realises the computation of the congestion control information without a cell delay.
Publisher
IEE-INST ELEC ENG
Issue Date
2001-12
Language
ENG
Citation

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, v.148, no.6, pp.323 - 327

ISSN
1350-2409
DOI
10.1049/ip-cds:20010622
URI
http://hdl.handle.net/10203/84672
Appears in Collection
EE-Journal Papers(저널논문)
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