A high-resolution synchronous mirror delay using successive approximation register

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD [1]. Fine locking is achieved by the successive approximation register for the sake of fast locking [2]. Measured results show that the maximum clock skew of the proposed SMD is 140 ps in the frequency range from 170 to 230 MHz and that the consumption power is 14.85 mW at 230 MHz in a 0.35-mum 1-poly 4-metal CMOS technology. The total locking time is 10 clock cycles.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2004-11
Language
ENG
Keywords

HIGH-SPEED DRAM; CLOCK GENERATOR; LOCKED LOOP; MICROPROCESSORS; CIRCUITS; RANGE

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.39, pp.1997 - 2004

ISSN
0018-9200
DOI
10.1109/JSSC.2004.835816
URI
http://hdl.handle.net/10203/84647
Appears in Collection
EE-Journal Papers(저널논문)
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