Fabrication of submicron Y-gate InP metal semiconductor field effect transistors using crystallographically defined contact technology

Abstract

Submicron Y-gate InP metal semiconductor field effect transistors (MESFETs), using a new crystallographically defined gate contact technology based on conventional optical lithography, are fabricated and their performances are investigated. In this technology, a new submicron gate patterning process has been developed based on the consistent crystallographic wet etching, characteristics of an InP dummy layer, which is grown on top of a conventional MESFET layer structure. The Y-shaped gate electrode, which is formed by the crystallographically etched sidewall profile of the double dummy layer structure, is used to realize InP MESFETs having 0.5 mum gate-foot dimension by controlling only the thickness of the InP dummy layer. The fabricated MESFETs using the proposed crystallographically defined gate contact technology show greatly improved overall device performances compared to conventional MESFETs. A maximum DC-transconductance of 234 mS/mm was measured and the maximum current gain cutoff frequency f(T) of 20 GHz and maximum oscillation frequency f(max) of 33 GHz were obtained from the devices fabricated using the proposed technology.