Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis

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This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IN from different sources and how to integrate the selected IN using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IN with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2002-06
Language
English
Article Type
Article
Keywords

EMBEDDED SYSTEMS; SELECTION

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.10, no.3, pp.240 - 252

ISSN
1063-8210
URI
http://hdl.handle.net/10203/83865
Appears in Collection
EE-Journal Papers(저널논문)
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