Hidden double data transfer scheme for MDL design

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dc.contributor.authorPark, SJko
dc.contributor.authorYoo, Hoi-Junko
dc.date.accessioned2013-03-04T18:32:07Z-
dc.date.available2013-03-04T18:32:07Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2001-05-
dc.identifier.citationELECTRONICS LETTERS, v.37, no.11, pp.676 - 677-
dc.identifier.issn0013-5194-
dc.identifier.urihttp://hdl.handle.net/10203/83642-
dc.description.abstractA high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with locally divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% Faster read access. It can be used as a general design framwork to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 mum DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory.-
dc.languageEnglish-
dc.publisherIEE-INST ELEC ENG-
dc.titleHidden double data transfer scheme for MDL design-
dc.typeArticle-
dc.identifier.wosid000169192000008-
dc.identifier.scopusid2-s2.0-0035942623-
dc.type.rimsART-
dc.citation.volume37-
dc.citation.issue11-
dc.citation.beginningpage676-
dc.citation.endingpage677-
dc.citation.publicationnameELECTRONICS LETTERS-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorPark, SJ-
dc.type.journalArticleArticle-
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EE-Journal Papers(저널논문)
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