DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, SJ | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2013-03-04T18:32:07Z | - |
dc.date.available | 2013-03-04T18:32:07Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-05 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.37, no.11, pp.676 - 677 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/83642 | - |
dc.description.abstract | A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with locally divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% Faster read access. It can be used as a general design framwork to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 mum DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory. | - |
dc.language | English | - |
dc.publisher | IEE-INST ELEC ENG | - |
dc.title | Hidden double data transfer scheme for MDL design | - |
dc.type | Article | - |
dc.identifier.wosid | 000169192000008 | - |
dc.identifier.scopusid | 2-s2.0-0035942623 | - |
dc.type.rims | ART | - |
dc.citation.volume | 37 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 676 | - |
dc.citation.endingpage | 677 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Park, SJ | - |
dc.type.journalArticle | Article | - |
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