Hidden double data transfer scheme for MDL design

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A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with locally divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% Faster read access. It can be used as a general design framwork to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 mum DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory.
Publisher
IEE-INST ELEC ENG
Issue Date
2001-05
Language
English
Article Type
Article
Citation

ELECTRONICS LETTERS, v.37, no.11, pp.676 - 677

ISSN
0013-5194
URI
http://hdl.handle.net/10203/83642
Appears in Collection
EE-Journal Papers(저널논문)
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