Low-power and high-performance equality comparator using pseudo-NMOS NAND gates
An equality comparator (EC), which exploits the fact that unequal cases happen more frequently in compare operations, is proposed. It is composed of conditional pseudo-NMOS NAND gates to save the power of the unused sub-ECs. The proposed 64-bit EC results in 31% faster speed and 42% less power dissipation than the conventional dynamic EC.
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Issue Date
- 2004-09
- Language
- English
- Article Type
- Article
- Citation
ELECTRONICS LETTERS, v.40, pp.1100 - 1101
- ISSN
- 0013-5194
- Appears in Collection
- EE-Journal Papers(저널논문)
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