TPartition: Testbench partitioning for hardware-accelerated functional verification
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, YI | ko |
| dc.contributor.author | Kyung, Chong-Min | ko |
| dc.date.accessioned | 2013-03-04T13:59:40Z | - |
| dc.date.available | 2013-03-04T13:59:40Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2004 | - |
| dc.identifier.citation | IEEE DESIGN TEST OF COMPUTERS, v.21, no.6, pp.484 - 493 | - |
| dc.identifier.issn | 0740-7475 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/82865 | - |
| dc.description.abstract | This hybrid dynamic simulation scheme implements part of the stimulator in software running on a processor and maps the rest onto a programmable hardware accelerator. an algorithm for hardware synthesis of behavioural testbenches enables better partitions resulting in lower communication costs between the two components. | - |
| dc.language | English | - |
| dc.publisher | IEEE COMPUTER SOC | - |
| dc.title | TPartition: Testbench partitioning for hardware-accelerated functional verification | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000225077200004 | - |
| dc.identifier.scopusid | 2-s2.0-11244258435 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 21 | - |
| dc.citation.issue | 6 | - |
| dc.citation.beginningpage | 484 | - |
| dc.citation.endingpage | 493 | - |
| dc.citation.publicationname | IEEE DESIGN TEST OF COMPUTERS | - |
| dc.contributor.localauthor | Kyung, Chong-Min | - |
| dc.contributor.nonIdAuthor | Kim, YI | - |
| dc.type.journalArticle | Article | - |
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