TPartition: Testbench partitioning for hardware-accelerated functional verification

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This hybrid dynamic simulation scheme implements part of the stimulator in software running on a processor and maps the rest onto a programmable hardware accelerator. an algorithm for hardware synthesis of behavioural testbenches enables better partitions resulting in lower communication costs between the two components.
Publisher
IEEE COMPUTER SOC
Issue Date
2004
Language
English
Article Type
Article
Citation

IEEE DESIGN TEST OF COMPUTERS, v.21, no.6, pp.484 - 493

ISSN
0740-7475
URI
http://hdl.handle.net/10203/82865
Appears in Collection
EE-Journal Papers(저널논문)
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