Dependability estimation of a digital system with consideration of software masking effects on hardware faults

Abstract

Based on the Very High Speed integrated Circuit (VHSIC) Hardware Description Language (VHDL), a simulation model for fault injection was developed to estimate the dependability of the digital system in operational phase. Through the fault injection into the simulation model, the software masking effect on hardware faults was investigated in this work. This effect was measured as software coverage function of hardware faults. The faults consist of the single bit-flip and stuck-at-x faults in the internal registers of the processor and in memory cells. Fault location reaches all registers and memory cells. In the simulation, fault distribution over locations is randomly chosen based on a uniform probability distribution. The type of injected faults (transient or permanent) is selected according to the ratio of transient faults to permanent ones in components. We developed the discrete reliability function to include the software coverage function of hardware faults in the estimation of the dependability of the digital system. Using the simulation model, we have predicted the software coverage values for the hardware faults in a digital system-interposing Logic System (ILS) in a nuclear power plant and estimated the reliability. Four operational profiles of the digital system were considered in this work to evaluate the dependency of system on operational profile. The results indicated that the software coverage value affects the reliability of the system. The software masking effect on hardware faults, therefore, should be properly considered for predicting the system dependability accurately in the operation phase. (C) 2001 Published by Elsevier Science Ltd.