SAPICE: A design tool of CMOS operational amplifiers

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Based on a new search strategy using circuit simulation and simulated annealing with local search, a design tool is proposed to automate design or tuning process for CMOS operational amplifiers. A special-purpose circuit simulator and some heuristics are used to accomplish the design within reasonable time. For arbitrary circuit topology and specifications, the discrete optimization of cost function is performed by global and local search. Through the comparision of design results and the design of a low-power high-speed CMOS operational amplifier usable in 10-b 25-MHz pipelined A/D converters, it has been demonstrated that this tool can be used for designing high-performance operational amplifiers with less design knowledge and effort.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
1997-09
Language
English
Article Type
Article
Keywords

MOS-TRANSISTORS; OPTIMIZATION; CIRCUITS; SYSTEM; 10-B

Citation

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E80A, no.9, pp.1667 - 1675

ISSN
0916-8508
URI
http://hdl.handle.net/10203/75883
Appears in Collection
EE-Journal Papers(저널논문)
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