DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yim, JS | ko |
dc.contributor.author | Kyung, Chong-Min | ko |
dc.date.accessioned | 2013-03-02T22:12:02Z | - |
dc.date.available | 2013-03-02T22:12:02Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1999-10 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.35, no.21, pp.1788 - 1789 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/75801 | - |
dc.description.abstract | While existing datapath compilers generate the same size buffer for all bits, in real datapaths, the load capacitance fluctuates according to the bit position, which leads to a nonuniform bit delay with unnecessarily high power consumption. This Letter proposes a datapath layout compiler using a bit-wise cell sizing, scheme that reduces the power consumption by equalising the delay of each bit position to the critical bit delay. Experimental results using the example of a real microprocessor have demonstrated a power consumption saving using the tri-state bus of 12% on average, compared to conventional datapaths using a uniform-size cell. | - |
dc.language | English | - |
dc.publisher | IEE-INST ELEC ENG | - |
dc.title | Datapath layout compiler using bit-wise cell-sizing scheme for delay balancing and power minimisation | - |
dc.type | Article | - |
dc.identifier.wosid | 000083436900003 | - |
dc.identifier.scopusid | 2-s2.0-85047674958 | - |
dc.type.rims | ART | - |
dc.citation.volume | 35 | - |
dc.citation.issue | 21 | - |
dc.citation.beginningpage | 1788 | - |
dc.citation.endingpage | 1789 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.nonIdAuthor | Yim, JS | - |
dc.type.journalArticle | Article | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.