Hardware-software co-implementation of a H.263 video codec

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In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of the H.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD) obtained fi-om the motion estimator.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2000-02
Language
English
Article Type
Article
Keywords

DISCRETE COSINE TRANSFORM

Citation

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.46, no.1, pp.191 - 200

ISSN
0098-3063
URI
http://hdl.handle.net/10203/75552
Appears in Collection
EE-Journal Papers(저널논문)
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