Node sampling technique to speed up probability-based power estimation methods

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 227
  • Download : 0
DC FieldValueLanguage
dc.contributor.authorhoon choiko
dc.contributor.authorseung ho hwnagko
dc.date.accessioned2013-03-02T17:27:29Z-
dc.date.available2013-03-02T17:27:29Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1998-06-
dc.identifier.citationELECTRONICS LETTERS, v.34, no.13, pp.1286 - 1287-
dc.identifier.issn0013-5194-
dc.identifier.urihttp://hdl.handle.net/10203/74714-
dc.description.abstractA new technique, node sampling, is proposed, to speed up probability-based power estimation methods. This technique samples and processes only a small portion of the total nodes to estimate the power consumption of a circuit. It is different from previous speed-up techniques for probability-based methods which reduce the processing time for each node, and is also different from the sampling techniques for simulation-based methods which sample input vector sequences. The experimental results demonstrate the validity of the proposed method.-
dc.languageEnglish-
dc.publisherInst Engineering Technology-Iet-
dc.titleNode sampling technique to speed up probability-based power estimation methods-
dc.typeArticle-
dc.identifier.wosid000074957600011-
dc.identifier.scopusid2-s2.0-0032090598-
dc.type.rimsART-
dc.citation.volume34-
dc.citation.issue13-
dc.citation.beginningpage1286-
dc.citation.endingpage1287-
dc.citation.publicationnameELECTRONICS LETTERS-
dc.identifier.doi10.1049/el:19980940-
dc.contributor.localauthorseung ho hwnag-
dc.contributor.nonIdAuthorhoon choi-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
Appears in Collection
RIMS Journal Papers
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0