DC Field | Value | Language |
---|---|---|
dc.contributor.author | hoon choi | ko |
dc.contributor.author | seung ho hwnag | ko |
dc.date.accessioned | 2013-03-02T17:27:29Z | - |
dc.date.available | 2013-03-02T17:27:29Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1998-06 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.34, no.13, pp.1286 - 1287 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/74714 | - |
dc.description.abstract | A new technique, node sampling, is proposed, to speed up probability-based power estimation methods. This technique samples and processes only a small portion of the total nodes to estimate the power consumption of a circuit. It is different from previous speed-up techniques for probability-based methods which reduce the processing time for each node, and is also different from the sampling techniques for simulation-based methods which sample input vector sequences. The experimental results demonstrate the validity of the proposed method. | - |
dc.language | English | - |
dc.publisher | Inst Engineering Technology-Iet | - |
dc.title | Node sampling technique to speed up probability-based power estimation methods | - |
dc.type | Article | - |
dc.identifier.wosid | 000074957600011 | - |
dc.identifier.scopusid | 2-s2.0-0032090598 | - |
dc.type.rims | ART | - |
dc.citation.volume | 34 | - |
dc.citation.issue | 13 | - |
dc.citation.beginningpage | 1286 | - |
dc.citation.endingpage | 1287 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el:19980940 | - |
dc.contributor.localauthor | seung ho hwnag | - |
dc.contributor.nonIdAuthor | hoon choi | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
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