A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V-cc = 2.0 V and 25 degrees C, The chip employs 1) a merged multibank architecture to minimize die area; 2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; 3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and 4) a block redundancy scheme with increased flexibility, The nonstitched chip with an area of 652 mm(2) has been fabricated using 0.16 mu m four-poly, four-metal CMOS process technology.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
1996-11
Language
ENG
Keywords

500-MEGABYTE/S

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.31, no.11, pp.1635 - 1644

ISSN
0018-9200
URI
http://hdl.handle.net/10203/74701
Appears in Collection
EE-Journal Papers(저널논문)
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