A virtual cache architecture for retaining the process working sets in a multiprogramming environment

A direct-mapped cache takes less time for accessing data than a set-associative cache because the time needed for selecting a cache line among the set is not necessary. The hit ratio of a direct-mapped cache, however, is lower due to the conflict misses caused by mapping multiple addresses to the same cache line. Addressing cache memory by virtual addresses reduces the cache access time by eliminating the time needed for address translation. The synonym problem in virtual cache necessitates an additional held in the cache tag to denote the process to which cache line belongs. In this paper, we propose a new virtual cache architecture whose average access time is almost the same as the direct-mapped cache while the hit ratio is the same as the set-associative caches. A victim for cache replacement is selected from those that belong to a process which is most remote from being scheduled. The entire cache memory is divided into n banks, and each process is assigned to a bank. Then, each process runs on the assigned bank, and the cache behaves like a direct-mapped cache. Trace-driven simulations confirm that the new scheme removes almost as many conflict misses as does the set-associative cache, while cache access time is similar to a direct-mapped cache.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
1996-12
Language
ENG
Citation

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E79D, no.12, pp.1637 - 1645

ISSN
0916-8532
URI
http://hdl.handle.net/10203/73153
Appears in Collection
NE-Journal Papers(저널논문)
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