Fast lock-on time mixed mode DLL with 10ps jitter

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A fast lock-on time mixed mode delay locked loop (DLL)is proposed to eliminate phase error in two steps. A digital fixed delay line compensates for the initial large phase error and an analogue voltage controlled delay line compensates for the small static phase error, resulting in low jitter. The lock-on time of the DLL is less than 10 clock cycles and the simulated jitter is below 10ps at 200MHz.
Publisher
IEE-INST ELEC ENG
Issue Date
1999-09
Language
English
Article Type
Article
Keywords

PLL

Citation

ELECTRONICS LETTERS, v.35, no.20, pp.1700 - 1701

ISSN
0013-5194
URI
http://hdl.handle.net/10203/72546
Appears in Collection
EE-Journal Papers(저널논문)
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