Event suppression by optimizing VHDL programs

The performance and efficiency of event-driven simulations, such as VHDL and Verilog simulation, depend on the number of events that occur during the simulation. In this paper, we classify events into two categories, sensitive events and insensitive events, according to the necessity of simulations, and show classification algorithms for both combinational circuits and sequential circuits. We also implement the optimization methodology that eliminates unnecessary simulation activity caused by the insensitive events. VHDL programs can be rewritten by augmenting suppressed sensitivity lists. Experiments show that the optimized VHDL programs run almost two times faster than the original ones.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
1998-08
Language
ENG
Keywords

CIRCUITS

Citation

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.17, no.8, pp.682 - 691

ISSN
0278-0070
URI
http://hdl.handle.net/10203/71481
Appears in Collection
EE-Journal Papers(저널논문)
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