A spacer patterning technology for nanoscale CMOS

Abstract

A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CND film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also pro-tides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.