Nanoscale CMOS spacer FinFET for the terabit era

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dc.contributor.authorChoi, Yang-Kyuko
dc.contributor.authorKing, TJko
dc.contributor.authorHu, CMko
dc.date.accessioned2007-06-27T06:25:56Z-
dc.date.available2007-06-27T06:25:56Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2002-01-
dc.identifier.citationIEEE ELECTRON DEVICE LETTERS, v.23, no.1, pp.25 - 27-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10203/688-
dc.description.abstractA spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices.-
dc.description.sponsorshipThe authors would like to thank the University of California- Berkeley Microlab staffs for their support in device fabrication.en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleNanoscale CMOS spacer FinFET for the terabit era-
dc.typeArticle-
dc.identifier.wosid000173259800009-
dc.identifier.scopusid2-s2.0-0036163060-
dc.type.rimsART-
dc.citation.volume23-
dc.citation.issue1-
dc.citation.beginningpage25-
dc.citation.endingpage27-
dc.citation.publicationnameIEEE ELECTRON DEVICE LETTERS-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorKing, TJ-
dc.contributor.nonIdAuthorHu, CM-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorchemical mechanical polishing (CMP)-
dc.subject.keywordAuthorcritical dimension (CD)-
dc.subject.keywordAuthordouble-gate-
dc.subject.keywordAuthorfinFET-
dc.subject.keywordAuthorgate planarization-
dc.subject.keywordAuthornanoscale CMOS-
dc.subject.keywordAuthorsilicon-on-insulator (SOI)-
dc.subject.keywordAuthorspacer etch-
dc.subject.keywordAuthorspacer lithography-
dc.subject.keywordAuthorthin-body-
dc.subject.keywordAuthoruniformity-
dc.subject.keywordPlusMOSFET-
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