Nanoscale CMOS spacer FinFET for the terabit era

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A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2002-01
Language
English
Article Type
Article
Citation

IEEE ELECTRON DEVICE LETTERS, v.23, no.1, pp.25 - 27

ISSN
0741-3106
URI
http://hdl.handle.net/10203/688
Appears in Collection
EE-Journal Papers(저널논문)
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