THE EFFECT OF INTERNAL PARASITIC CAPACITANCES IN SERIES-CONNECTED MOS STRUCTURE

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dc.contributor.authorLEE, SHko
dc.contributor.authorPARK, SBko
dc.contributor.authorPark, Kyu Hoko
dc.date.accessioned2013-02-27T13:13:42Z-
dc.date.available2013-02-27T13:13:42Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1995-01-
dc.identifier.citationIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E78A, no.1, pp.142 - 145-
dc.identifier.issn0916-8508-
dc.identifier.urihttp://hdl.handle.net/10203/68778-
dc.description.abstractA simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.-
dc.languageEnglish-
dc.publisherIEICE-INST ELECTRON INFO COMMUN ENG-
dc.titleTHE EFFECT OF INTERNAL PARASITIC CAPACITANCES IN SERIES-CONNECTED MOS STRUCTURE-
dc.typeArticle-
dc.identifier.wosidA1995QD76200022-
dc.identifier.scopusid2-s2.0-0029208124-
dc.type.rimsART-
dc.citation.volumeE78A-
dc.citation.issue1-
dc.citation.beginningpage142-
dc.citation.endingpage145-
dc.citation.publicationnameIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES-
dc.contributor.localauthorPark, Kyu Ho-
dc.contributor.nonIdAuthorLEE, SH-
dc.contributor.nonIdAuthorPARK, SB-
dc.type.journalArticleLetter-
dc.subject.keywordAuthorCOMPUTER AIDED DESIGN (CAD)-
dc.subject.keywordAuthorMODELING AND SIMULATION, PARASITIC CAPACITANCE-
dc.subject.keywordAuthorDELAY MODEL-
dc.subject.keywordAuthorSERIES-CONNECTED MOS STRUCTURE-
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EE-Journal Papers(저널논문)
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