Extremely scaled silicon nano-CMOS devices

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2003-11
Language
ENG
Keywords

WORK FUNCTION; INVERSION-LAYERS; NANOSCALE CMOS; SI MOSFETS; GATE; TECHNOLOGY; METAL; MOBILITY; TRANSISTOR; FINFET

Citation

PROCEEDINGS OF THE IEEE, v.91, no.11, pp.1860 - 1873

ISSN
0018-9219
DOI
10.1109/JPROC.2003.818336
URI
http://hdl.handle.net/10203/687
Appears in Collection
EE-Journal Papers(저널논문)
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