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Please use this identifier to cite or link to this item:
http://hdl.handle.net/10203/687
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| Hit : 935 Download : 112 |
Title | Extremely Scaled Silicon Nano-CMOS Devices |
Authors | CHANG, LELAND; CHOI, YANG-KYU; HA, DAEWON; RANADE, PUSHKAR; XIONG, SHIYING; BOKOR, JEFFREY; HU, CHENMING; KING, TSU-JAE |
Keywords | CMOS; FinFET; metal gate; molybdenum; MOSFET; nanotechnology; scaling; ultrathin body (UTB) |
Issue Date | Nov-2003 |
Publisher | IEEE |
Citation | Proceedings of the IEEE, v.91, no.11, pp.1860-1873 |
Abstract | Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations. |
ISSN | 0018-9219 |
URI | http://hdl.handle.net/10203/687 |
Appears in Collections |
| Files in This Item: | Description | Size | Format | |
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| Extremely%20scaled%20silicon%20nano-CMOS%20devices.pdf | 1152Kb | Adobe PDF | View/Open | |
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