A Low-Noise, Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in Less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over ail operating frequency range.
Publisher
IEEE-Inst Electrical Electronics Engineers Inc
Issue Date
2000-08
Language
ENG
Article Type
Article
Keywords

DPLL; CMOS

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.8, pp.1137 - 1145

ISSN
0018-9200
URI
http://hdl.handle.net/10203/67762
Appears in Collection
RIMS Journal Papers
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