A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter, a prototype PLL fabricated in a 0.6-mu m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method. The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.
Publisher
IEEE-Inst Electrical Electronics Engineers Inc
Issue Date
2000-06
Language
ENG
Article Type
Article
Keywords

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Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.6, pp.807 - 815

ISSN
0018-9200
URI
http://hdl.handle.net/10203/67760
Appears in Collection
RIMS Journal Papers
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