Power-efficient gate control of synchronous boost converters with high output voltage

A half output voltage swing gate driving scheme is presented for high voltage single chip DC/DC converters. In the proposed scheme the energy for the PMOS gate drive is reused for the NMOS gate drive, and switching loss is reduced. A high speed and area-efficient high voltage level shifter is also realised. A prototype is implemented using a 0.5 mu m 40 V power BiCMOS process.
Publisher
INST ENGINEERING TECHNOLOGY-IET
Issue Date
2007-02
Language
ENG
Citation

ELECTRONICS LETTERS, v.43, pp.156 - 157

ISSN
0013-5194
DOI
10.1049/el:20072929
URI
http://hdl.handle.net/10203/6754
Appears in Collection
EE-Journal Papers(저널논문)
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