The formation of a SiO2 layer at the Ta2O5/Si interface is observed by annealing in dry O2 or N2 and the thickness of this layer increases with an increase in annealing temperature. Leakage current of thin (less than 40 nm thick) Ta2O5 films decreases as the annealing temperature increases when annealed in dry O2 or N2. The dielectric constant vs annealing temperature curve shows a maximum peak at 750 or 800-degrees-C resulting from the crystallization of Ta2O5. The effect is larger in thicker Ta2O5 films. But the dielectric constant decreases when annealed at higher temperature due to the formation and growth of a SiO2 layer at the interface. The flat band voltage and gate voltage instability as a function of annealing temperature can be explained in terms of the growth of interfacial SiO2. The electrical properties of Ta2O5 as a function of annealing conditions do not depend on the fabrication method of Ta2O5 but strongly depend on the thickness of Ta2O5 layer.